Field of the Invention
The present invention relates to a semiconductor device used for a power module with high breakdown voltage of 600V or more and a method of manufacturing the semiconductor device.
Description of the Background Art
Conventionally, in order to reduce recovery loss EREC and reverse recovery current Irr in a diode, impurity concentration of a p-type anode layer is lowered to reduce injection efficiency of holes serving as carriers to be injected from the p-type anode layer into an n-type cathode layer. In such a technique, at the time of forming the p-type anode layer of the diode it is common to combine a process of implanting boron ions into the surface of a wafer and a process of high-temperature diffusion, so that the p-type anode layer with a low impurity concentration such as boron is made thin.
Also, conventionally, at the time of incorporating a diode chip in a power module, it is common to use a technique in which a diode chip is electrically connected to another component such as an Insulated Gate Bipolar Transistor (IGBT) chip by bonding a wire on an anode electrode formed directly on a p-type anode layer (see Japanese Patent Application Laid-Open No. 2015-213193, for example).
In the case where a foreign substance with high hardness, such as silicon, exists in or on an anode electrode at the time of bonding a wire on the anode electrode, the foreign substance may get caught between the anode electrode and the wire, which causes the surface of a p-type anode layer to be damaged by a crack or the like. This results in deterioration of device characteristics, such as reduction in the breakdown voltage and the breakdown strength of the diode. In addition, the p-type anode layer having a low impurity concentration is susceptible to such a crack. On the other hand, Japanese Patent Application Laid-Open No. 2015-213193 fails to mention any countermeasure against a crack that may occur when a wire is bonded on the anode electrode.
As described above, conventional diodes cannot achieve either reduction in recovery loss EREC and reverse recovery current Irr or suppression of the influence of a crack generated at the time of wire bonding at the same time.